AHLGREN, David J.
Department of Engineering, Trinity College Hartford, CT 06106 USA dahlgren@trincoll.edu
Abstract: Since 1994, students in ENGR 221L (Digital Circuits and Systems) at Trinity College have successfully used complex programmable logic devices (CPLDs) in their final design projects. They carry out their projects primarily in VHDL, used in conjunction with Altera's Max + Plus II CAD running on HP9000 UNIX workstations (the same tools are available on PCs).
Course projects carried out in the fall of 1998 included:
The focus on solving large problems promotes student teamwork and gives them the opportunity to use such modern approaches as hierarchical design and concurrent engineering and to gain exposure to commercial CAD tools. The paper presents the educational approaches and a sequence of laboratory exercises that enable students to extend their knowledge beyond what is the norm in the introductory course. Specific educational outcomes are also discussed.
Keywords: digital, design, CAD, CPLD, teamwork
This paper reports on the educational strategies employed and outcomes achieved by exposing students to VHDL and complex programmable logic devices (CPLDs) in the introductory computer engineering course at Trinity College. The paper also describes projects carried out by students during the most recent offering of the course (Fall, 1998). The paper argues that significant educational benefits accompany the introduction of sophisticated computer-aided design (CAD) tools in the introductory course. Introduction of such allows students to solve large problems in short time frames. Constraints of time and complexity make it opportune for students to work in teams that employ hierarchical design and concurrent engineering approaches supported by the chosen CAD tools. This experience encourages students to apply these methods in later courses and in senior design projects required for the engineering degree.
The paper describes projects undertaken by students in Fall, 1998: two "tiny" four-bit CPUs, each designed by a team of six students; an energy-efficient washroom for campgrounds; and a digital interface for an ultraviolet flame sensor.
Mainly second-year engineering students take the introductory computer engineering course at Trinity College, ENGR 221L (Digital Circuits and Systems), but the course also attracts students from all four college classes and from other majors (e.g., computer science). ENGR 221L meets three times each week in one-hour lecture sections and once a week for three hours in the laboratory. From this course students develop expertise in digital design that includes basic knowledge (abilities 1-7 below) and enhanced basic knowledge (abilities 8-10 below):
a basic working knowledge of Boolean logic, gate circuitry, flip-flops and registers, memory devices, and finite-state machines,
an ability to develop digital circuitry using standard synthesis tools (Karnaugh maps, state transition diagrams, and state tables),
a facility with using CAD tools to carry out schematic capture, simulation, and synthesis,
an ability to build, test, and verify digital circuits,
familiarity with basic programmable logic devices and a hardware description language (ABEL or CUPL),
the ability to work effectively on a lab team,
the ability to summarize and explain experimental work by writing clear and complete laboratory reports,
an ability to work on a large team-based project that requires use of hierarchical design and concurrent engineering methods,
considerable experience in the use of an advanced CAD toolset,
a working knowledge of a useful subset of VHDL.
The course develops students' basic abilities (1-7) mainly through a series of laboratory design projects carried out in the first half of the term. These projects include the design of traffic light controllers, adders and subtractors, and a communications network with parity checking. In this work students use a schematic capture and simulation program B^2 Logic that is sold by Beige Bag Software, Ann Arbor, Michigan, USA. With B^2 Logic students enter and verify their LSTTL-based designs before building the hardware circuits, increasing efficiency and the likelihood of success.
In realizing abilities (8-10), a working knowledge of a standard hardware description language (here VHDL) is essential. In ENGR 221L, VHDL is not identified as a separate subject of study. Rather, the course introduces VHDL through a series of examples; whenever the course introduces hardware elements, it also presents the corresponding VHDL descriptions. In this way, students naturally learn to describe with VHDL such circuits as gates, multiplexers, decoders, flip-flops, counters, registers, and finite-state machines. These examples introduce a language subset sufficient to develop CPLD based designs. This subset consists of the VHDL constructs: ENTITY, ARCHITECTURE, SIGNAL, TYPE, PORT, PROCESS, IF-THEN-ELSE, CASE..WHEN, WHEN...ELSE conditional assignment structure, and 'EVENT.
The first four lab projects introduce students to the basics of applying standard synthesis methods for combinational logic (e.g., Karnaugh Maps), using Beige Bag Software's B^Logic, and wiring and debugging circuits on a breadboard. The fifth lab design--a 4-bit adder/subtractor--was built first using LSTTL chips. As a bridge connecting the early labs to the later ones, the next experiment required students to develop the same adder/subtractor using the Max + Plus II graphic editor using LSTTL equivalent cells from the Altera library. They also designed a BCD-to-seven segment decoder with VHDL and the modules together using the Max + Plus II graphic editor. Following successful simulation of the overall system, students programmed the design into a single Altera EPM5032 device and tested the programmed chip. In the next lab, students improved a skeletal design for an arithmetic logic unit (ALU) by increasing the word size and adding new logical operations. This exercise paved the way for the CPU221/98 final design project. From these VHDL exercises, students gained appreciation for the productivity increase that results from the use of VHDL and CPLDs. As a result, Max + Plus II and VHDL became the preferred design tools for the rest of the semester.
With the background provided by these exercises, students were able to tackle their final design projects using Max + Plus II, VHDL, and Altera CPLDs. Handed out four weeks before the end of the term, the assignment included project suggestions, but it encouraged students to develop their own topics. Students had worked in pairs throughout the term, a pattern they were expected to continue. To work on final design projects, pairs could be combined with other pairs to form larger teams. The project assignment was handed out on November 13, and the final project and documentation was due on December 14. In addition to the CPU design, project suggestions included a vending machine, digital stopwatch, calculator, camera shutter speed tester, and serial ASCII interface. Of the eighteen enrolled students in 1998, two teams of six students worked on CPU designs, two students worked on a CPLD-based keyboard encoder, and two others designed electronics for an automated washroom. Two students chose to work alone; one developed a digital clock, and the second designed a CPLD-based flame-sensor interface. The following sections describe three of these projects.
The goal of this design project was to develop a digital controller for an energy-efficient campground washroom. The system aimed to minimize electric power consumed by hand dryers and electrical lighting and water consumption in sinks and showers. To detect the presence of a person, the students used IR proximity sensors at sinks and dryers, motion sensors in shower stalls, and a second set of motion sensors to control room lighting. As part of this project, they also designed a coin-operated vending machine to collect payments for showers and a timer to limit the duration of a shower.
Students segmented this design into a number of finite-state machines. The sinks, hand dryers, and electric lights were controlled by simple two-state FSMs that produced on/off outputs in response to input signals from motion detectors or proximity sensors. The FSM associated with the shower responded to enable signals provided by the vending machine, the shower timers, and motion control sensors. In this way, the shower would be turned off automatically when time ran out or when the person left the shower.
Students developed VHDL descriptions of all circuitry and carried out full verification using the Max + Plus II CAD tools. The design fit in an Altera EPM7032LC44 CPLD and required the equivalent of approximately 500 logic gates. The first programmed chip was fully operational.
This project was motivated by the need to develop a sensitive flame detector for a fire-fighting mobile robot. The Hammamatsu R2868 ultraviolet sensor is sensitive to a narrow band of of radiation that is typical of flame. An interface circuit, provided with the sensor, generates an output pulse train whose period decreases with increasing flame intensity. At the highest UV intensities, the period was about 50 milliseconds.
The student developed VHDL codes describing a presettable time-base and counter to measure the oscillation period. The counter's output drove an A/D converter chip (Analog Devices AD 557) to realize a 0-5 Volt analog interface to the robot's microcontroller. The interface was contained in a single Altera EPM7032LC44 CPLD, occupying nearly all of the device (equivalent to 600 logic gates.) This circuit will be used on fire-fighting mobile robots currently under development.
Students in ENGR221L have designed four-bit 'tiny' CPUs each year since 1994. The project has developed a reputation as a challenging design experience. (Experiences with earlier projects were reported in [1] and [2].) The CPU design problem required students to develop a four-bit processor that interfaces to a RAM chip for data storage and an EEPROM chip that contains a program. The project introduced many new topics including memory addressing and decoding, bus timing; development of simple machine-level programs, and computer organization.
The instructor distributed a handout that described an initial design that students were encouraged to improve. The handout included a system block diagram, description of main modules (ALU, address logic, bi-directional data bus interface, control unit, etc.) along with a timing diagram showing the two-phase system clock and the timing of control unit state transitions and system-wide multiplexer enable signals. In addition, the handout proposed an initial arrangement of registers (accumulator A, temporary register B, address register MAR, program counter PC, status register SR, and index register X), and an initial instruction set and op-code arrangement (Table 1). The handout included a planning matrix that students could use to list the register transfers needed at each clock cycle, for each machine level instruction. By completing this matrix, students gained a complete understanding of control unit and data path timing; from it they could generate Boolean expressions for all key control and MUX enable signals in the system. Students also received sample program listings including machine codes for adding and subtracting integers, and codes for more complex tasks including copying and sorting arrays.
Table I: Initial Instruction Set
| Instruction | Mnemonic | Opcode |
| Load A immediate | LDAI | 0000 |
| Load A direct | LDAD | 0001 |
| Load A indexed | LDAX | 0010 |
| Add immediate | ADDI | 0011 |
| Add indexed | ADDX | 0100 |
| NAND indexed | NANDX | 0101 |
| Store A direct | STAD | 0110 |
| Store A indexed | STAX | 0111 |
| NAND immediate | NANDI | 1000 |
| Unused | * | 1001 |
| Load X immediate | LDXI | 1010 |
| Load X direct | LDXD | 1011 |
| Store X direct | STXD | 1100 |
| Update X Immediate | UDXI | 1101 |
| Branch uncond'l | BRA | 1110 |
| Branch if zero | BEQ | 1111 |
The first CPU design team expanded the address bus to eight bits, from seven. The CPU design was segmented into modules--addressing logic, ALU, data bus bidirectional interface, and control logic. Pairs of students on this team took responsibility for developing and verifying one or two modules. After all modules were simulated using Max + Plus II, the team assembled them and verified the resulting top-level design using Max + Plus II. The CPU design fit in a single Altera EPM9320LC84 CPLD, requiring the equivalent of approximately 5000 logic gates.
This team built a complete working "tiny" computer by adding ROM and RAM elements. The highest address in the addressing space (FF hexadecimal) was allocated to an input/output port. This I/O capability allowed the team to use their machine in a feedback control application. In that application, a software program, written with the team's version of the instruction set, varied the duty cycle of the current through an LED so that its brightness matched that of a second LED, which served as a brightness standard. The intensity of each LED was monitored by a phototransistor, and an analog comparator chip compared the outputs of the two phototransistors. When the comparator indicated that the brightness was too low, it was increased, and vice-versa. Some brightness matching was achieved, but closed-loop response was too slow. As the semester closed, team members were reviewing their machine codes and investigating timing issues related to the comparator chip.
The second CPU221/98 design team's CPU, Sleepbuster '98, was fully designed and verified with Max + Plus II. The team envisioned using Sleepbuster '98 as a controller in a home security system. The various sub-systems of the CPU chip were verified independently as was the assembled CPU design. The design was programmed into an Altera EPM9320LC84 device and connected to ROM and RAM chips on the breadboard. Simple programs stored in the ROM executed correctly in the hardware. However, the security system software did not operate as expected, and the team was not able to debug it during the available time. Thus, this team met with mixed success.
Nevertheless, students were extremely positive about their experiences, as the following excerpts from the teams' project reports indicate:
(Team 1): Overall, the CPU project was an invaluable learning experience. It brought together all of the concepts, lab work, and experience gained in digital fundamentals. It also shed light on new circuit implementation techniques such as (feedback) control and memory mapping. This is a small taste of what future engineering courses will bring...
(Team 2): ..the CPU project was a tremendous learning experience. Although the security system program did not run as expected, the project enabled us to achieve a strong understanding of CPU design that is applicable to any future computer design project. The CPU design project has given us a new understanding of the internal functionality of any computer and the process that a computer goes through in order to run a program from its memory. This project also tied in many of the applications of the individual subjects of study in ENGR 221L such as RAM, ROM, decoders, registers, multiplexers, buffers, and ALUs. This project never would have been possible without Altera programmable technology and MAX + Plus II software.
The examples cited in this paper show that the introduction of VHDL and CPLD-based design in the introductory courses increases the range of projects that beginning computer engineering students can address successfully. Students in ENGR 221L developed a working knowledge of CPLD-based design and the use of VHDL as a means for describing and synthesizing digital systems. The CAD toolset used in the course, Altera's Max + Plus II, enabled team-based concurrent engineering of sub-systems to be integrated hierarchically. Using these CAD approaches, students have completed large projects that could not be approached using classical digital design methods in short time frames. Completion of such projects motivates students to elect higher-level courses and to engage in more complex VHDL-based projects.
The Altera University Program provides CPLDs and the Max + Plus II development tools free of charge to universities. Contact Altera through the e-mail address university@altera.com or via the Web at http://www.altera.com. There are no charges to the school for software support and maintenance. Enrollment in the University Program is straightforward and may be accomplished through the Web site. Altera provides multiple copies of Max + Plus II software and documentation, support for hardware description languages and interfaces to other electronic design tools. Max + Plus II runs on appropriately-configured PCs equipped with Windows '95 or '98 or Windows NT, and on HP, Sun SPARC, and IBM RISC 6000 machines that run UNIX. The reference [3] includes a number of VHDL templates that have helped ENGR221L students to understand language syntax and structure, and the texts [4]-[7] have proved to be valuable references.
The author acknowledges the continuing support of Altera, Inc. and recognizes the hard work of ENGR221L students and their teaching assistants, Amir Tamrakar and Sheldon Provost. The author is especially indebted to Dr. Ronald LaComb, who taught the ENGR 221L laboratory in Fall, 1998.
[1] AHLGREN, D.J. CPLD-Oriented Design Projects for the First Course in Digital Systems., Proc. of the ASEE/IEEE Frontiers in Education Conference, Phoenix USA, 1998. 4 p.
[2] AHLGREN, D.J. CPLD-based Design in the Introductory Computer Engineering Course.Proc. of the ASEE Annual Conference, Milwaukee, 1997. 7 p.
[3} Max+Plus II VHDL. San Jose: Altera Corporation, 1997. 164 p.
[4] SKAHILL, K. VHDL for Programmable Logic. Boston: Addison Wesley, 1996. 593 p. ISBN 0-201-89573-0.
[5] SALCIC, Z. Digital Systems Design and Prototyping Using Field Programmable Logic. Boston: Kluwer Academic Publishers, 1997. 368 p. ISBN 0-7923-9935-8.
[6] SCARPINO, F. VHDL and AHDL Digital System Implementation. New York: Prentice-Hall, 1998. 336 p. ISBN 0-13-857087-6.
[7] ASHENDEN, P. The Designer's Guide to VHDL. San Francisco: Morgan-Kaufman, 1996. 688 p. ISBN 1-55860-270-4.