Figure 1.
CHANG, J. Morris
Computer Engineering Program and Dept. of Computer Science Illinois Institute of Technology 10 west 31st street, Chicago, IL 60616 chang@charlie.iit.edu http://www.iit.edu/~chang
* Partial support for this work was provided by the NationalScience Foundation's Division of Undergraduate Education through grant DUE-9650347.
Abstract: As the complexity of digital circuits increases continuously the cost of device testing has also increased sharply. To reduce the testing cost, the design and testing phase have become intertwined. Much of the testing strategy must be planned during the design phase. It is this integrated nature of design and testing that motivated this NSF-funded project. A laboratory that provides students an integral view of digital design and testing has been developed at IIT. This paper presents the experience we have gained from the project.
Keywords: computer engineering education, digital design, digital testing, hands-on laboratory.
Compared to the significant growth in the development of microchips, current electrical and computer engineering students do not receive enough training in the testing phase of the digital design life cycle. While colleges currently have many courses focusing primarily on digital design, most do not cover digital testing (at least not with a hands-on environment). This is primarily because testing equipment is very expensive and its usage requires professional training. Professional Automated Testing Equipment (ATE's) can cost millions of dollars, which is far out of the reach of most academic institutions. The premise of the Integrated Digital Design and Testing Laboratory (IDDTL) research project is to give engineering students the opportunity to not only design integrated circuits, but to learn how to test their designs.
IDDTL offers a cost effective approach for colleges to add the integration of digital design and testing to their curriculum. IDDTL is based on a virtual automated testing equipment (VATE) system we have created. Using the VATE system, students can test and validate actual chips manufactured (or by using programmable logic chips) from their designs. The VATE system is comprised of off-the-shelf hardware components which are readily available at a reasonable price, and a software system designed to give engineering students the opportunity to learn the essentials of testing their digital designs. The hardware and software are wrapped into a laboratory package which includes an example curriculum that can be modified to fit in to an existing class, or to be used to create a new one.
Students can use existing digital design and simulation packages to create and simulate their designs, and then load these in to our easy to use VATE graphical software package where they can test their designs. The student can set up tests and run them on the VATE hardware (typically a pattern generator and logic analyzer system), thereby learning the fundamentals of the testing process. The laboratory effectively simulates high priced professional testing equipment currently used in the industry, and provides students with a new perspective of digital design, where an integral view of the design and the testing processes is presented.
In the digital design course, students will develop these crucial skills through classroom lectures and hands-on experiments in the laboratory. To address these issues in a complex design and yet make it possible to be completed within a semester, we choose the implementation of a RISC CPU as the driver.
Reduced Instruction Set Computer (RISC) concepts, which emerged in the early 1980s, can be found in many modern computer systems. In this course we implement the MIPS instruction set on CPLDs (Complex Programmable Logic Devices). The definition of MIPS instructions can be found in a widely used textbook (by Patterson and Hennessy [3]). This modern architecture employs a fixed length instruction set which eases the decoding process. No microprogramming is involved. This load/store architecture has three instruction classes (register-to-register operation, load/store and branch) which use two different instruction formats. A complete instruction set encoding can be found in the textbook. Thus, the reason why we choose MIPS are clear — modern architecture, simplicity and complete description.
To cope with the complexity of a CPU, we use the industrial standard hardware description language - VHDL (IEEE 1076). Without any prior experience, students get familiar with a widely used commercially available VHDL tool - Maxplus2 (from Altera) through weekly hands-on laboratory assignments. Combining VHDL and logic synthesis [1][2] allows our students to focus on a high level abstraction in digital systems and leave the detailed implementations to CAD tools. Mastering this enabling technology not only makes it possible to design a CPU as the final project in a senior level course but also gives our students an edge in the job marketplace. The hardware and software are acquired through a grant from Altera’s University Program.
We invest eight weeks (i.e. more than half of the semester) in covering the industry standard language, VHDL (IEEE-1076). Basic components of digital systems and their VHDL implementations are reviewed at this time. Advanced topics, such as synthesis issues, portability issues and LPMs (Library of Parameterized Modules) are also covered within this eight weeks. Students are taught on basic theory (e.g. how to build a system with primitive components) and industrial practice (e.g. how to use a vendor-supplied megafunctions in their designs).
Five weeks are allocated for CPU architecture and instruction set. Datapath design and timing at the block diagram level are introduced. It is worth noting that as the functionality of each block is described, students can quickly identify its implementation. This is mainly due to the hands-on experience they gained in the first eight weeks. Application specific instructions (e.g. for Multimedia application) are also introduced.
Testing theory and practice are covered in the last two weeks. Partial scan, ATPG (Automatic Test Pattern generation), partitioning (to improve the controllability and observability) and Boundary Scan are introduced. Finally, the operation of ATE (Automatic Test Equipment) is presented.
To complement the classroom lecture, we employ a commercially available CAD tool (Maxplus2 from Altera) in a set of hands-on weekly laboratory experiments. These labs, in concert with a semester design project, provide our students with a progressive path from a simple adder to a RISC CPU. The course notes we developed are closely coupled with lab material. All the examples are synthesizable with the CAD tool.
As the complexity of digital circuits increases continuously, the cost of device testing has also increased sharply. The increasing complexity of testing has shifted more and more of the testing responsibility towards the design engineers. Unfortunately, current engineering education is negligent in focusing on this trend. Students mistakenly learn that design and testing are orthogonal processes.
With the help of programmable devices, students can bypass the waiting period for IC fabrication and obtain ASIC designs after the devices have been programmed. Adding a testing facility into our digital design laboratories will enable our students to have a complete perspective of digital design and testing. The students can experience the testing issues from a designer’s view.
This section addresses the testing facility that is under development at IIT. This Virtual Automatic Test Equipment (Virtual ATE) is built from off-the-shelf components and is an affordable and innovative solution for university engineering departments. With this ATE, students can test and validate actual chips built from their designs. The Virtual ATE (shown in the next figure) effectively simulates the multi-million dollar testing equipment currently used by industry.
Figure 1.
A working prototype of the proposed virtual ATE (Automatic Test Equipment) system has been developed at IIT. This VATE is based on a HP Logic Analyzer and Pattern Generator. The prototype system accepts simulation output from Maxplus2 and generates SCPI (Standard Commands for Programmable Instrument) commands to configure the Pattern Generator and Logic Analyzer through the GPIB (IEEE-488) interface. The DUT (Device Under Test) receives stimulus from the patter generator and generates output response to the Logic Analyzer. The actual response captured by the Logic Analyzer will be fed into software (based on HP VEE) for further processing. The current system can display a graphical comparison of the expected output waveforms (from the simulation) and the actual response waveforms (from logic analyzer) through HP VEE. For more information about this project, please visit our web site: http://www.iit.edu/~iddt.
The prototype system is working in the laboratory. One of the features that is under development is to facilitate boundary scan (IEEE Std. 1149.1). Most of the high density (and usually high pin count) PLDs feature boundary scan today. As CPU pin count increases continuously, the cost of device testing has also increased sharply. This demands a much more expensive ATE, since the cost of ATE is proportional to the number of the pins it can handle. Boundary scan provides an alternative in testing for high pin count devices. With Virtual ATE, students will be able to work with this industrial standard on their final CPU designs.
This course was introduced for the first time in the Spring 1996. We had access to a lab with computers with Pentium-90MHZ CPU and 16 Mbyte memory. The largest CPLD device we had access to was FLEX 8K family. In order to fit the CPU design into a single chip, the datapath was limited to 8-bit wide. The compilation time for the final project ranged from 40 to 50 minutes. We concluded that more powerful machines and higher density devices are crucial to this course.
Fortunately, technology has advanced drastically since then. In Spring 1997, we acquired a brand new lab equipped with new computers (Pentium Pro 180MHZ and 32 Mbyte memory). Meantime, the CPLD density has almost been doubled (Moore’s law again; circuit density doubles every 18 months or so). This time, we expanded the data path to 16-bit wide. The compilation time (for the final project) ranged from 8 to 15 minutes. This becomes much more manageable for the final project. Computer hardware has become much more affordable lately. In 1998, we upgrade the memory to 64 Mbyte. Earlier this year, we have added newer machines with faster CPU (AMD K6-II 350MHZ ). The compilation time for the final project ranged from 5 to 10 minutes.
It is worth noting that the VHDL tools for CPLD design are still evolving (the VHDL tool in Maxplus2 was introduced in late 1994). Within the past two years, new features were introduced, through the software new release, almost every quarter. For example, the VHDL constructs — generic and LPMs were not fully supported until the middle of Spring 1997. In addition to the software upgrade in the laboratory, course notes must be constantly updated with the latest material. This creates an exciting and dynamic learning environment for both teacher and student.
A senior design course that placed a RISC CPU design in the context of currently available components (e.g. CPLDs) and modern design methodologies (e.g. VHDL) is presented. The high quality commercially available CAD tool (with toll free technical support!) and updated computer facility provide an environment that is similar to the industrial setting.
The weekly lab assignment provides a progressive and hands-on learning experience to our students. These labs, in concert with a semester design project, provide our students with a smooth transition from the abstractions of academe to the realities of engineering practice. An integrated digital design and testing laboratory reinforce the concept of design-for-testability.
A cost effective approach for colleges to add the integration of digital design and testing to their curriculum is presented. Using the VATE system, students can test and validate actual chips from their designs. Such laboratory setting provides our students an integral view of digital design and testing.
The University Program at Altera Corporation provided us with the software (Maxplus2) and hardware (CPLDs) used in digital design courses at Illinois Institute of Technology. Partial support for this work has also been provided by the Undergraduate College of Illinois Institute of Technology.
| [1] | J. M. CHANG. From VHDL to CPLD - a Synthesizable Journey. workshop presented in IEEE International ASIC Conference, Austin, Texas, Sept. 21, 1995. |
| [2] | J. M. CHANG. Teaching Top-Down Design using VHDL and CPLD. Proceedings of IEEE Frontiers in Education Conference, Salt Lake City, Utah, November 6-9, 1996. |
| [3] | D. PATERSON and J. HENNESSY, Computer Organization & Design The Hardware/Software Interface, Morgan Kaufmann, 1994. |